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Preliminary
RF2690
W-CDMA RECEIVE AGC AND DEMODULATOR
7
Typical Applications
* W-CDMA Systems
Product Description
The RF2690 is an integrated complete IF AGC amplifier and quadrature demodulator designed for the receive section of W-CDMA applications. It is designed to amplify received IF signals, while providing 70dB of gain control range, a total of 90dB gain, and demodulation to baseband I and Q signals. This circuit is designed as part of RFMD's single mode W-CDMA chipset, which includes the RF9678 as modulator and IF AGC and the RF2638 as upconvertor. The IC is manufactured on an advanced 25GHz FT Silicon Bi-CMOS process, and is packaged in a 20-pin, 4mmx4mm, leadless chip carrier.
1.00 0.90 0.60 0.24 typ
4.00 sq.
0.65 0.30
4 PLCS
3 0.20
2.10 sq.
12 MAX 0.05
Dimensions in mm.
0.75 0.50 0.50 Note orientation of package. 0.23 0.13
4 PLCS
7
QUADRATURE DEMODULATORS
NOTES: 1 Shaded lead is Pin 1. 2 Pin 1 identifier must exist on top surface of package by identification mark or feature on the package body. Exact shape and size is optional. Dimension applies to plated terminal: to be measured between 0.02 mm and 0.25 mm from terminal end. 4 Package Warpage: 0.05 mm max. 5 Die Thickness Allowable: 0.305 mm max. 3
Optimum Technology Matching(R) Applied
Package Style: LCC, 20-Pin, 4x4
uSi Bi-CMOS
Si BJT
GaAs HBT SiGe HBT
VGC2 VGC1
GaAs MESFET Si CMOS
Features
* Digitally Controlled Power Down Mode * 2.7V to 3.3V Operation
14 I OUT+ 13 I OUT-
20 NC 2 NC 3
1
17
18
IF+
IF-
Gain Control
* Digital LO Quadrature Divide-by-4 * IF AGC Amp with 70dB Gain Control * 80dB Maximum Voltage Gain
W-CDMA IN+ 4 I/Q W-CDMA IN- 5 Cal
15 ENCAL 16 FCLK 12 Q OUT+ Div 4 Mode Control & Biasing 11 Q OUT-
19 VREF2V
6 VCC
8 LO
7 GND
9 EN WUP
10 EN RX
Ordering Information
RF2690 RF2690 PCBA W-CDMA Receive AGC and Demodulator Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev A4 010918
7-39
RF2690
Absolute Maximum Ratings Parameter
Supply Voltage Power Down Voltage (VPD) Input RF Power Ambient Operating Temperature Storage Temperature
Preliminary
Rating
-0.5 to +5 -0.5 to VCC +0.7 +3 -40 to +85 -40 to +150
Unit
VDC VDC dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall Inputs and AGC
IF Frequency W-CDMA IF Input Impedance
Specification Min. Typ. Max.
Unit
Condition
Temp=25C, VCC =3V, ZLOAD =60k diff., LO=760MHz@-10dBm, ZSOURCE =500 diff.
190 1200 2400
MHz
Single-ended Balance. An external resistor across the differential input is used to define the input impedance.
7
QUADRATURE DEMODULATORS
LO Frequency LO Input Level LO Input Impedance Maximum Voltage Gain
-20 76
760 -10 50 81
0
MHz dBm dB
Single-ended. Pin-to-Pin voltage gain. Note: 10dB additional voltage gain in input match 50 to 500.
Minimum Voltage Gain Gain Variation versus VCC and Temperature Gain Control Voltage Input IP3
5 -3 0.3
12 +1
15 +3 2.4
dB V Defined with external 10k resistor in series with VGC1 pin. Analog gain control. Blockers at 10MHz and 20MHz offset. Maximum Gain. VGC =2.4V Minimum Gain. VGC =0.3V Maximum Gain. VGC =2.4V Measured differentially. Out of band blocker causing 1dB of inband gain compression. Blocker at 5MHz. Maximum Gain. VGC =2.4V Minimum Gain. VGC =0.3V Butterworth third order, FC 2.5M+10% Calibrated. FCLK =13MHz A measure of IQ gain match and IQ quadrature accuracy. Measured for baseband frequencies 100kHz to 2.5MHz. Resistive Load Impedance. Differentially across pins. Capacitive Load Impedance. To ground. VGC =0.3V, PIN =-40dBm VGC =0.3V, PIN =-40dBm
-52 Noise Figure Inband Output 1dB Compression Compression
1.5
-48 -5 5 2.0
0
dBm dBm dB VP-P
-48 -17 Baseband 3dB Bandwidth Sideband Suppression 2.25 2.5 2.75 27
dBm dBm MHz dB
DC Offset Baseband External Load
20
+40 60 5
mV k pF V dB degree
Output DC Voltage IQ Amplitude Balance IQ Phase Balance
VCC -1.3
VCC -1.6 +0.2 +2
VCC -1.9 +0.5 +5
7-40
Rev A4 010918
Preliminary
Parameter
Auto Calibration
FCLK Input Frequency1 FCLK Signal Level FCLK Pin Input Impedance Calibration Time Current, Auto Cal. Current, Once Auto Cal Finished CALEN 13 0.4 20 200 1 1 TBD 2.7 3.0 <1 5 8 1.8 0 VCC 0.5 3.3 V A mA mA V V 1.0 MHz VP-P k us mA uA Single-ended.
RF2690
Specification Min. Typ. Max. Unit Condition
Disabled after calibration.
DC Specifications
Supply Voltage Current Consumption Power Down W-CDMA Warm-up W-CDMA Logic Levels VEN High Voltage VEN Low Voltage
1
Bondout option available for 15.36MHz, 18MHz and 19MHz.
7
QUADRATURE DEMODULATORS
Rev A4 010918
7-41
RF2690
Preliminary
Auto Calibration Mode The filters are automatically tuned when the ENCAL pin goes high. The filters are reset to a nominal value whenever the ENCAL pin goes low. The auto calibration circuitry is independent of the EN WUP and the EN RX control pins. The EN RX and ENCAL pins can be connected together if desired. Mode Control Truth Table
Mode Power Down W-CDMA RX Warm-Up W-CDMA RX EN RX 0 1 1 EN WUP X 0 1
Logic
EN RX EN WUP Chip Enable Warm-up Enable If EN RX=0, then entire IC is powered down. If EN WUP=0, then IC is in warm-up mode.
7
QUADRATURE DEMODULATORS
7-42
Rev A4 010918
Preliminary
Pin 1 2 3 4 Function VGC1 NC NC W-CDMA IN+ Description
Analog gain control. Valid control voltage ranges are from 0.5V to 2.5V. These voltages are valid with a 10k resistor in series with GC pin. Unused. Connect to signal ground in application. Unused. Connect to signal ground in application. W-CDMA balanced input pin. This pin is internally DC-biased and should be DC-blocked if connected to a device with a DC level present. For single-ended input operation, one pin is used as an input and the other W-CDMA input is AC coupled to ground. The balanced input impedance is 2.4k, while the single-ended input impedance is 1.2k.
RF2690
Interface Schematic
BIAS
BIAS
1200
1200
W-CDMA IN+
W-CDMA IN-
5 6 7 8
W-CDMA INVCC GND LO
Same as pin 4, except complementary input. Supply Connect to ground. LO input pin. This input is internally DC-biased and should be DCblocked if connected to a device with DC present. The frequency of the signal applied to this pin is internally divided by a factor of four, hence the LO applied should be four times the frequency of the IF. Warm-up mode enable. The input LO buffers and divider chains are enabled. When logic "low" (<0.5V), chip is in warm-up mode. When logic "high" (VCC -0.3V), chip is in W-CDMA RX mode. Chip enable. Power down. When logic "low" (<0.5V), all circuits are turned off. When logic "high" (VCC -0.3V), all circuits are operating. Complementary output to Q OUT+. Balanced baseband output of Q mixer. This pin is internally DC-biased and should be DC-blocked externally. The output may be used singleended by leaving one of the pins unconnected, however half of the output voltage will be lost.
See pin 4.
7
QUADRATURE DEMODULATORS
Q OUT+ 150 A Q OUT150 A
9 10 11 12
EN WUP EN RX Q OUTQ OUT+
VCC
VCC
13 14
I OUTI OUT+
Complementary output to I OUT+. Balanced baseband output.
VCC VCC
I OUT+ 150 A I OUT150 A
15 16
ENCAL FCLK
Calibration enable. FCLK clock reference for the automatic calibration circuitry.
20 k
17 18
IFIF+
Complementary output to IF+. IF test point output. This balanced node is pinned out to allow for monitoring of the AGC output signal as it enters the demodulator. During normal operation, this pin and its complementary output should be left floating and not connected.
Rev A4 010918
7-43
RF2690
Pin 19 20 Pkg Base Function VREF2V VGC2 Die Flag Description
2V voltage reference decouple (i.e., 10nF to ground). Gain control decouple (i.e., 10nF to ground). Ground.
Preliminary
Interface Schematic
7
QUADRATURE DEMODULATORS
7-44
Rev A4 010918
Preliminary
Application Notes
RF2690
Voltage Gain Measurement Set-up The evaluation board uses a unity voltage gain Op-Amp to simulate the 60k differential load impedance condition for the chip. The 50 output impedance of Op-Amp makes the use of a 50 spectrum analyzer power measurement possible. The power gain measured will be considered as RAW Gain. The input impedance of the chip is 500 differential by adding a parallel 680 resistor. The input transformer matches 50 to 500 and results in 10dB difference between voltage gain and power gain, hence, the voltage gain of the chip is RAW Gain minus 10dB. Because the input transformer loss is 0.8dB, it needs to be added to the gain. Since the Op-Amp has the unity voltage gain, the voltage at the evaluation board output is the same as the voltage at chip I or Q output. Therefore, the voltage gain of the chip with 60k load can be calculated by Gv=RAW Gain-10+0.8(dB) Input IP3 Measurement The input IP3 measurement is based on a two tone inter-modulation test condition from the 3GPP standard, which specifies two tones with offset frequencies at 10MHz and 20MHz. Due to the on-chip baseband filtering, the two tone output is attenuated and cannot be seen. Since the only parameter observable is the IM3 product, the input IP3 then is calculated by IIP3=Pin+0.5*(Pin+RAW Gain-IM3) Noise Figure Measurement The noise figure measurement is based on the noise figure definition NF=NO -NI -Gain, where NO is the output noise density, NI is the input noise density (-174dBm/Hz when no input signal is applied) and Gain is the RAW Gain. The output noise density NO is measured at 1MHz offset when no signal input is applied. The NF is calculated by NF=NO 174dBm/Hz-RAW Gain. Since the I and Q re-combination will provide 3dB extra for signal-to-noise ratio, the actual noise figure is should be reduced by 3dB. In addition, noise figure should be reduced by the input transformer loss of 0.8dB. Therefore, the NF is calculated by NF=NO +174-RAW Gain-3-0.8(dB) 1dB Gain Compression Point Voltage at Baseband Output The device has a relatively constant 1dB gain compression point versus VGC. Gain compression is tested with a CW signal with 60k load differential. How to Calculate the Power Gain of the Demodulator In the system analysis for cascaded gain, noise and IP, it is often required to calculate the power gain of the demodulator chip itself in matched load condition. Below is an example on how to determine this power gain value. For this example, the load impedance is 60k differential, the output AC impedance of the I or Q port is 500, the measured RAW Gain is 95dB. First, the power gain from the input of the chip to the input of Op-Amp needs to be calculated. Since the voltage at the 50 load and the voltage at Op-Amp input are the same, the difference of the power gain across the Op-Amp is the ratio of load impedances. Hence, the power gain to the Op-Amp input is 95dB-10log(60000/50)=95-30=65dB. Second, the power gain of the demodulator itself with matched load is calculated. The mismatch coefficient a is determined by the mismatch coefficient equation
7
QUADRATURE DEMODULATORS
4R S R L 4 500 60000 = 10 log ------------------------- = 10 log ------------------------------------- = - 15dB 2 2 ( R S + RL ) ( 500 + 60000 )
Rev A4 010918
7-45
RF2690
Preliminary
Since the power gain to the input of the Op-Amp GP'=GP, where GP is the power gain of demodulator for matched load. Therefore, the demodulator power gain is 65+15=80dB. AC Coupling in Evaluation Board The output I and Q baseband signal is AC coupled for evaluation purposes only. The high-pass corner frequency is at 1/(2 RC)=1/(6.28*30k*100nF)=56Hz. I and Q Output DC Voltage and Its Offset Although the I and Q output is AC coupled on the evaluation board, in most applications, it would be DC coupled to the ADC input buffer. The DC voltage at the IC output is VCC -1.6V with a possible variation of 0.3V due to temperature and tolerance. The differential circuit asymmetry would cause common mode DC offset to the extent of 40mV. Baseband Filter Calibration Process The BB (baseband) filter calibration process is same for both WCDMA and GSM/DCS. After calibration is done, the WCDMA mode sets the circuitry to have a 3dB bandwidth of 2.5MHz, the GSM/DCS mode (if the chip has GSM/DCS mode) sets the circuitry to have a 3dB bandwidth of 250kHz. The BB filter in the I and Q path needs to be calculated every time after power down. When the FCLK pin is connected to a signal generator with 0dBm output level at 13.0MHz, a logic high at CALEN pin for 200s will calibrate the filter to have 2.5MHz bandwidth with 10% accuracy when WCDMA mode is set, or to 250kHz bandwidth with 10% accuracy when GSM mode is set. The calibration is done when the chip is powered on only. Calibration is independent from all other conditions, e.g. the chip enable could be off. The calibration circuitry consumes 400A. When the calibration sequence is complete after 200s, the ICC drops to 0mA. The 3dB bandwidth is defined to be from the reference level at 1MHz for WCDMA and at 50kHz for GSM/DCS. The 3dB bandwidth is independent of VGC and VCC. The filter can also be calibrated with different clock frequencies from 10MHz to 30MHz to tune the bandwidth over -40% to +60% from its default 3dB bandwidth (2.5MHz for WCDMA and 250kHz for GSM). The 3dB bandwidth is linear with clock frequency.
7
QUADRATURE DEMODULATORS
7-46
Rev A4 010918
Preliminary
Pin Out
VREF2V VGC2 IF+ FCLK IF-
RF2690
* VGC1 1 NC 2 NC 3 W-CDMA IN+ 4 W-CDMA IN- 5 *
20
19
18
17
16
* 15 ENCAL 14 I OUT+ 13 I OUT12 Q OUT+ 11 Q OUT-
6 VCC
7 GND
8 LO
9 EN WUP
10 EN RX
* * Represents "GND".
7
QUADRATURE DEMODULATORS
Rev A4 010918
7-47
RF2690
Application Schematic
VREF 2V
Preliminary
10 nF FCLK 10 nF 10 pF
20 10 k VGC 1
19
18
17
16 15 ENCAL
2
14 100 nF
I OUT P
3
13 100 nF
I OUT N
W-CDMA 10 nF
4
12 100 nF
Q OUT P
7
QUADRATURE DEMODULATORS
10 nF 2.4 k Balanced
5 6 7 8 9 10
11 100 nF
Q OUT N
EN RX 10 nF VCC EN WUP 1 nF LO IN
7-48
Rev A4 010918
Preliminary
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
JP3 +5V -5V C21 1 uF(16V) + + 1 2 3 C22 1 uF(16V) CON3 C11 10 pF C8 1 nF C9 100 pF TP4 I OUT P TP1 VREF2V TP2 IFP TP3 IFN
Drawing 2690400 Rev -
RF2690
J3 FCLK
ENCAL
+5V C14 100 nF C12 100 nF R12* DNI C13 100 nF R14 20 k
U2 7 3 + 8 6
R1 10 k VGC
* 1 2 3 4
20
19
18
17
16
* 15 14 13 12 11 TP6 Q OUT P R13* DNI
R2 10 k R3 10 k
50 strip R18 51 C15 100 nF
J5 IOUT -5V
2
4 CLC426
5
TP5 I OUT N
J2 WCDMA
C2 5.1 pF 50 strip C4* DNI
L2 150 nH C6 100 pF
R7 680
5 * 6 7 8 9 10
C18 100 nF C19 100 nF
R4 10 k R5 10 k
R15 20 k +5V C16 100 nF R16 20 k
7 U3 8 6 3 +
*
50 strip R19 51 C17 100 nF
J6 QOUT -5V
2
4 CLC426
5
JP1 8 7 6 5 4 3 2 1 HDR 8 VCC + C7 1 uF R10 1M R9 1M R8 1M VGC C10 ENRX 10 nF VCC ENCAL ENWUP C20 100 pF C23* DNI ENWUP ENRX TP7 Q OUT N
R17 20 k
50 strip C24* DNI
J4 LO IN
7
QUADRATURE DEMODULATORS
Rev A4 010918
7-49
RF2690
Evaluation Board Layout Board Size 3.1" x 3.0"
Board Thickness 0.032", Board Material FR-4
Preliminary
7
QUADRATURE DEMODULATORS
7-50
Rev A4 010918
Preliminary
RF2690
7
QUADRATURE DEMODULATORS
Rev A4 010918
7-51
RF2690
IGC versus VGC
15.0
(IF Freq. 190MHz LO Freq. 760MHz VCC=3.0V Temp. 25oC)
Preliminary
Voltage Gain versus POUT (1dB Compression)
(VCC=3.0V, VGC=2.4V, IF=191MHz, LO=760MHz @ -10dBm)
81.0 80.0 79.0 Voltage Gain [dB]
10.0
Igc [uA]
5.0 78.0
Voltage Gain (dB)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
0.0
77.0 76.0 75.0 74.0 73.0 72.0
IGC (uA)
-5.0
-10.0
-15.0
-20.0 71.0 -25.0 70.0 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700
VGC (V)
Power Out (mV-peak)
NF versus VGC
Voltage Gain versus VGC (Temp. +25oC, - 40oC, +85oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm,VCC=2.7V,VGC=2.4V to 0.3V) 90.0 Gain @2.7V,Temp.+25C Gain @2.7V,Temp.- 40C Gain @2.7V,Temp.+85C
7
QUADRATURE DEMODULATORS
70.0
IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.0, VGC=2.4 to 0.3V)
60.0
NF[dB]
80.0 70.0
50.0
NF (dB)
40.0
Voltage Gain (dB)
60.0 50.0 40.0 30.0 20.0
30.0
20.0
10.0
10.0 0.0 0.3 0.7 1.1 1.5 1.9 2.3 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
0.0
Vgc (V)
VGC (V)
W-CDMA Baseband Filter Response (Calibrated)
(IF=190MHz to 195MHz, LO=760MHz @ -10dBm, VCC=3.0V, VGC=2.4V)
8.0 80.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Power Out [dBm] 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 90.0
Voltage Gain versus VGC (Temp. +25oC, - 40oC, +85oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.0V, VGC=2.4V to 0.3V)
Gain @3.0V,Temp.+25C Gain @3.0V,Temp.- 40C Gain @3.0V,Temp.+85C
Amplitude (dBm)
Voltage Gain (dB)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Frequency (MHz)
VGC (V)
7-52
Rev A4 010918
Preliminary
Voltage Gain versus VGC (Temp.+25C, - 40C, +85oC)
IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, VGC=2.4V to 0.3v)
90.0 Gain @3.3V,Temp.25C 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Gain @3.3V,Temp.- 40C Gain @3.3V,Temp.+85C 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 90.0 80.0 Gain @3.3V,Temp.+85C Gain @3.0V,Temp.+85C Gain @2.7V,Temp.+85C
RF2690
Voltage Gain versus VGC (Temp. +85oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0V, 2.7V, VGC=2.4V to 0.3V)
Voltage Gain (dB)
Voltage Gain (dB)
1.6
1.8
2.0
2.2
2.4
VGC (V)
VGC (V)
Voltage Gain versus VGC (Temp. -40oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0V, 2.7V, VGC=2.4V to 0.3V)
IIP3 versus VGC (Temp. +25oC, - 40oC, +85oC)
(IF Freq.190MHz, LO Freq. 760MHz @ -10dBm, VCC=2.7V, V GC=2.4V to 0.3V)
90.0 10.0 80.0 70.0 60.0 50.0 40.0 30.0 -40.0 20.0 10.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 -50.0 Gain @3.3V,Temp.- 40C Gain @3.0V,Temp.- 40C Gain @2.7V,Temp.- 40C 0.0
7
QUADRATURE DEMODULATORS
2.4 2.4 IIP3 @2.7V,Temp.+25C IIP3 @2.7V,Temp.- 40C IIP3 @2.7V,Temp. +85C
-10.0
Voltage Gain (dB)
IIP3 (dBm)
-20.0
-30.0
-60.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
VGC (VGC)
VGC (V)
Voltage Gain versus VGC (Temp. 25oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0V, 2.7V & VGC=2.4V to 0.3V)
IIP3 versus VGC (Temp. +25oC, - 40oC, +85oC)
IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.0V, VGC=2.4V to 0.3V)
90.0 Gain @3.3V,Temp.25C 80.0 70.0 60.0 Gain @3.0V,Temp.25C Gain @2.7V,Temp.25C
10.0 IIP3 @3.0V,Temp.25C IIP3 @3.0V,Temp.- 40C IIP3 @3.0V,Temp.+85C
0.0
-10.0
Voltage Gain (dB)
IIP3 (dBm)
50.0 40.0 30.0
-20.0
-30.0
-40.0 20.0 -50.0 10.0 0.0 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 -60.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
VGC (V)
VGC(VGC)
Rev A4 010918
7-53
RF2690
IIP3 versus VGC (Temp. +25oC, - 40oC, +85oC)
10.0
Preliminary
IIP3 versus VGC (Temp. +85oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0V, 2.7V, VGC=2.4V to 0.3V)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, VGC=2.4V to 0.3V)
IIP3 @3.3V,Temp.25C IIP3 @3.3V,Temp.- 40C IIP3 @3.3V,Temp. +85C
5.0 0.0 -5.0 IIP3 @3.3V,Temp. +85C IIP3 @3.0V,Temp.+85C IIP3 @2.7V,Temp. +85C
0.0
-10.0
-10.0 -15.0
IIP3 (dBm)
IIP3 (dBm)
-20.0
-20.0 -25.0 -30.0
-30.0
-40.0
-35.0 -40.0 -45.0
-50.0
-60.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
-50.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC (V)
VGC (V)
IIP3 versus VGC (Temp. -40oC)
7
QUADRATURE DEMODULATORS
0.0
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V, 3.0V, 2.7V, VGC=2.4V to 0.3V)
-10.0
IIP3 @3.3V,Temp.- 40C IIP3 @3.0V,Temp.- 40C IIP3 @2.7V,Temp.- 40C
-20.0
IIP3 (dBm)
-30.0
-40.0
-50.0
-60.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
VGC (V)
IIP3 versus VGC (Temp. 25oC)
(IF Freq. 190MHz, LO Freq. 760MHz @ -10dBm, VCC=3.3V ,3.0V, 2.7V, VGC=2.4V to 0.3V)
0.0 -5.0 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 -50.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 IIP3 @3.3V,Temp.25C IIP3 @3.0V,Temp.25C IIP3 @2.7V,Temp.25C
IIP3 (dBm)
VGC (V)
7-54
Rev A4 010918

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